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(parent: edb1731) | patch
interconnect/csr_bus/SRAM: add mem_size check
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 1 Nov 2019 10:33:43 +0000 (11:33 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 1 Nov 2019 10:33:50 +0000 (11:33 +0100)
commit9c3c43c94ade654a1e386ff6dd131195dd6d63d7
tree03d0fb98123204827de7a84c4b969f861fc316fctree
parentedb1731ef98a35262e838cfbf08b75a611843bf5commit | diff
interconnect/csr_bus/SRAM: add mem_size check

Memory size is limited to 512 bytes:
- CSR region size is 0x800 (4096)
- default csr_data_width is 8
maximum size = 4096/8 = 512 bytes.
litex/soc/interconnect/csr_bus.py diff | blob | history