arch-riscv: Enable support for riscv 32-bit in SE mode.
authorAustin Harris <austinharris@utexas.edu>
Thu, 27 Dec 2018 01:19:00 +0000 (19:19 -0600)
committerAustin Harris <austin.dane.harris@gmail.com>
Thu, 7 Feb 2019 01:48:08 +0000 (01:48 +0000)
commit9c5373ca61587409e4d0f6ad4c032e8d53be28ca
tree21f173c01ba01f908b4eb449cf43b6b628081a91
parentea487f9bb7b35556a39ef25765859330e62b11ae
arch-riscv: Enable support for riscv 32-bit in SE mode.

This patch splits up the riscv SE mode support for 32 and 64-bit.
A future patch will add support for decoding rv32 instructions.

Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15355
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
src/arch/riscv/linux/linux.cc
src/arch/riscv/linux/linux.hh
src/arch/riscv/linux/process.cc
src/arch/riscv/linux/process.hh
src/arch/riscv/process.cc
src/arch/riscv/process.hh
src/arch/riscv/types.hh
src/base/loader/elf_object.cc
src/base/loader/object_file.hh
src/sim/process.cc