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(parent: f7ddc46) | patch
riscv: enable unaligned memory accesses
authorAlec Roelke <ar4jc@virginia.edu>
Tue, 21 Mar 2017 16:51:54 +0000 (12:51 -0400)
committerAlec Roelke <ar4jc@virginia.edu>
Wed, 5 Apr 2017 20:21:04 +0000 (20:21 +0000)
commit9d0c9ab12361e009796bdb0b5d074c98d3f75b0e
tree9bd47ef4af8035a833a676f6f76487b371b84b95tree
parentf7ddc4672a17ee4fab3011bb1b570cc7c17dff28commit | diff
riscv: enable unaligned memory accesses

Sometimes an ld instruction will be split across a
cache boundary.  Previously RISC-V was set to not
allow this.  This patch fixes that.

Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Reviewed-on: https://gem5-review.googlesource.com/2341
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
src/arch/riscv/isa_traits.hh diff | blob | history