freedreno/ir3: rewrite regmask to better support a6xx+
authorRob Clark <robdclark@chromium.org>
Mon, 24 Feb 2020 19:57:52 +0000 (11:57 -0800)
committerMarge Bot <eric+marge@anholt.net>
Fri, 28 Feb 2020 16:53:41 +0000 (16:53 +0000)
commit9d2aaa589cf1c4fc8599f26a033aeeabb595f134
tree0b5efc135ca97566de1cb30efed3ad65d3f00fd1
parentc02cd8afbd6a2f2b1aaaec9d499e6ede55aebe8c
freedreno/ir3: rewrite regmask to better support a6xx+

To avoid spurious sync flags, we want to, for a6xx+, operate in terms of
half-regs, with a full precision register testing the corresponding two
half-regs that it conflicts with.

And while we are at it, stop open-coding BITSET

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
src/freedreno/ir3/ir3.h