Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 20 May 2020 17:22:11 +0000 (18:22 +0100)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 20 May 2020 17:22:46 +0000 (18:22 +0100)
commit9d3afafccf1b176afd3ea143ff482ff8de21d6ab
treec8ad38d951c4742cdde77b2bb37cc4690e235345
parent6c43c8180f0a739849611c1efb8ad9266ff42ca5
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
5c/df2aad62cc8f92bc1afcf23e46df563cfeaeeb [new file with mode: 0644]