FPU: Implement floating convert from integer instructions
authorPaul Mackerras <paulus@ozlabs.org>
Thu, 16 Jul 2020 05:51:57 +0000 (15:51 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Thu, 3 Sep 2020 07:44:41 +0000 (17:44 +1000)
commit9e8fb293edd59f355cc1fd020f96dafee0af867c
tree1e1ef9aa231b8003c6afe96f2734d79c6b0c57b4
parentb628af6176bd0bfa0289fa823ec205f48988ec53
FPU: Implement floating convert from integer instructions

This implements fcfid, fcfidu, fcfids and fcfidus, which convert
64-bit integer values in an FPR into a floating-point value.
This brings in a lot of the datapath that will be needed in
future, including the shifter, adder, mask generator and
count-leading-zeroes logic, along with the machinery for rounding
to single-precision or double-precision, detecting inexact results,
signalling inexact-result exceptions, and updating result flags
in the FPSCR.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
decode1.vhdl
fpu.vhdl
tests/fpu/fpu.c
tests/test_fpu.bin
tests/test_fpu.console_out