projects / riscv-tests.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 30b70b7) | patch
Remove `set arch riscv:rv%d`
authorTim Newsome <tim@sifive.com>
Wed, 20 Dec 2017 23:00:01 +0000 (15:00 -0800)
committerTim Newsome <tim@sifive.com>
Wed, 20 Dec 2017 23:00:01 +0000 (15:00 -0800)
commit9eb3b8d3fcc7a491121c186e3a35022e11bb5653
tree89bd71c87806e26e603f042a83ccdd3d628c621ctree
parent30b70b7ed988fa06ab423e05b272898a1527ba11commit | diff
Remove `set arch riscv:rv%d`

gdb gets target XLEN from register width now, so this is taken care of
automatically.
debug/testlib.py diff | blob | history