[AArch64] SVE load/store_lanes support

[AArch64] SVE load/store_lanes support

This patch adds support for SVE LD[234], ST[234] and associated
structure modes.  Unlike Advanced SIMD, these modes are extra-long
vector modes instead of integer modes.

2018-01-13  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-modes.def: Define x2, x3 and x4 vector
	modes for SVE.
	* config/aarch64/aarch64-protos.h
	(aarch64_sve_struct_memory_operand_p): Declare.
	* config/aarch64/iterators.md (SVE_STRUCT): New mode iterator.
	(vector_count, insn_length, VSINGLE, vsingle): New mode attributes.
	(VPRED, vpred): Handle SVE structure modes.
	* config/aarch64/constraints.md (Utx): New constraint.
	* config/aarch64/predicates.md (aarch64_sve_struct_memory_operand)
	(aarch64_sve_struct_nonimmediate_operand): New predicates.
	* config/aarch64/aarch64.md (UNSPEC_LDN, UNSPEC_STN): New unspecs.
	* config/aarch64/aarch64-sve.md (mov<mode>, *aarch64_sve_mov<mode>_le)
	(*aarch64_sve_mov<mode>_be, pred_mov<mode>): New patterns for
	structure modes.  Split into pieces after RA.
	(vec_load_lanes<mode><vsingle>, vec_mask_load_lanes<mode><vsingle>)
	(vec_store_lanes<mode><vsingle>, vec_mask_store_lanes<mode><vsingle>):
	New patterns.
	* config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
	SVE structure modes.
	(aarch64_classify_address): Likewise.
	(sizetochar): Move earlier in file.
	(aarch64_print_operand): Handle SVE register lists.
	(aarch64_array_mode): New function.
	(aarch64_sve_struct_memory_operand_p): Likewise.
	(TARGET_ARRAY_MODE): Redefine.

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_vect_load_lanes):
	Return true for SVE too.
	* g++.dg/vect/pr36648.cc: XFAIL for variable-length vectors
	if load/store lanes are supported.
	* gcc.dg/vect/slp-10.c: Likewise.
	* gcc.dg/vect/slp-12c.c: Likewise.
	* gcc.dg/vect/slp-17.c: Likewise.
	* gcc.dg/vect/slp-33.c: Likewise.
	* gcc.dg/vect/slp-6.c: Likewise.
	* gcc.dg/vect/slp-cond-1.c: Likewise.
	* gcc.dg/vect/slp-multitypes-11-big-array.c: Likewise.
	* gcc.dg/vect/slp-multitypes-11.c: Likewise.
	* gcc.dg/vect/slp-multitypes-12.c: Likewise.
	* gcc.dg/vect/slp-perm-5.c: Remove XFAIL for variable-length SVE.
	* gcc.dg/vect/slp-perm-6.c: Likewise.
	* gcc.dg/vect/slp-perm-9.c: Likewise.
	* gcc.dg/vect/slp-reduc-6.c: Remove XFAIL for variable-length vectors.
	* gcc.dg/vect/vect-load-lanes-peeling-1.c: Expect an epilogue loop
	for variable-length vectors.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256618