Merge pull request #1623 from YosysHQ/mmicko/edif_attr
authorMiodrag Milanović <mmicko@gmail.com>
Tue, 14 Jan 2020 18:19:32 +0000 (19:19 +0100)
committerGitHub <noreply@github.com>
Tue, 14 Jan 2020 18:19:32 +0000 (19:19 +0100)
commit9fbeb57bbdb98265b541d7a62213e83de63c8a1a
treea095bc5fbcfe5a3007fc17b928887e4b9fe2cefa
parentca2f3db53f3f330d283079bf44b3cef6b7f197be
parentccfe1e5909ba6093e49ebdfaa1aac6c4aa267036
Merge pull request #1623 from YosysHQ/mmicko/edif_attr

Export wire properties in EDIF
techlibs/xilinx/synth_xilinx.cc