Speed up the divider a little
authorPaul Mackerras <paulus@ozlabs.org>
Mon, 23 Sep 2019 04:39:50 +0000 (14:39 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Mon, 23 Sep 2019 04:39:50 +0000 (14:39 +1000)
commita01ffaeb64f56c2e6a4cf5e990a66be6d9a74e51
tree28b5bea5bea6005887c72789c80c781622d8425a
parentd5bc6c882499e6644f9fa75fe4ddbeb0b5c49600
Speed up the divider a little

This looks for cases where the next 8 bits of the quotient are obviously
going to be zero, because the top 72 bits of the 128-bit dividend
register are all zero.  In those cases we shift 8 zero bits into the
quotient and increase count by 8.  We only do this if count < 56.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
divider.vhdl