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(parent: 27547e8) | patch
add PredicateBaseRM decode to CR Ops Simple mode as well as ff=3-bit
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 6 Oct 2022 12:16:28 +0000 (13:16 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 6 Oct 2022 12:16:28 +0000 (13:16 +0100)
commita082b25264bbb22527bda6e409b21223e8531c47
tree89affd5e8a9e1f181dbfd9bc60e845f8499690abtree
parent27547e8fad40836704f0902ce12b61170406be81commit | diff
add PredicateBaseRM decode to CR Ops Simple mode as well as ff=3-bit
src/openpower/decoder/power_insn.py diff | blob | history
src/openpower/sv/trans/svp64.py diff | blob | history
src/openpower/sv/trans/test_pysvp64dis.py diff | blob | history