fhdl/verilog: properly connect instance inouts
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Fri, 17 Feb 2012 10:08:41 +0000 (11:08 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Fri, 17 Feb 2012 10:08:41 +0000 (11:08 +0100)
commita1ad30faab428905349214643837a1deed861b20
tree3a799a33add3c83846eb9ccbeec6fc3c754617c6
parentca7056b07fb90b9424fa33918b5d701577e23be9
fhdl/verilog: properly connect instance inouts
migen/fhdl/verilog.py