back.{rtlil,verilog}: split convert_fragment() off convert().
authorwhitequark <whitequark@whitequark.org>
Mon, 19 Aug 2019 19:27:02 +0000 (19:27 +0000)
committerwhitequark <whitequark@whitequark.org>
Mon, 19 Aug 2019 19:49:51 +0000 (19:49 +0000)
commita2241fcfdb0bec6d3909d161e2b8ea5fb0ab924a
treeaecfa394beeed9931712b3ce1c6594416d4c2103
parent8e048c5a7ce0f6ca2c4ccebd64361a1029aa9637
back.{rtlil,verilog}: split convert_fragment() off convert().

Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.
nmigen/back/rtlil.py
nmigen/back/verilog.py
nmigen/compat/fhdl/verilog.py