x86: correct MPX insn w/o base or index encoding in 16-bit mode
authorJan Beulich <jbeulich@suse.com>
Fri, 6 Mar 2020 07:50:56 +0000 (08:50 +0100)
committerJan Beulich <jbeulich@suse.com>
Fri, 6 Mar 2020 07:50:56 +0000 (08:50 +0100)
commita23b33b3d131f240b2525d9a24831b33f2b43e26
tree99add9964f55a4b6ed0acd13a14388b09537ed91
parenta04973848dc529f4eeb3bd198251da9faf01e2a2
x86: correct MPX insn w/o base or index encoding in 16-bit mode

Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16
fails to match the templates.

The SDM leaves open whether BNDC[LNU] with a GPR operand require an
operand size override; this aspect is therefore left untouched here.
gas/ChangeLog
gas/config/tc-i386.c
gas/testsuite/gas/i386/i386.exp
gas/testsuite/gas/i386/mpx-16bit.d [new file with mode: 0644]
gas/testsuite/gas/i386/mpx-16bit.s [new file with mode: 0644]
opcodes/ChangeLog
opcodes/i386-dis.c