projects / nmigen.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9f40681) | patch
back.rtlil: prepare for Yosys sigspec slicing improvements.
authorwhitequark <cz@m-labs.hk>
Sun, 16 Dec 2018 18:03:14 +0000 (18:03 +0000)
committerwhitequark <cz@m-labs.hk>
Sun, 16 Dec 2018 18:03:14 +0000 (18:03 +0000)
commita3050ea80ebcdc7b860736f7692ef19c32f8ccc1
tree19bcef4863177aae012555806c712c660ef79958tree
parent9f40681fadcc8e217bb337276fa44a71df67ef0dcommit | diff
back.rtlil: prepare for Yosys sigspec slicing improvements.

See YosysHQ/yosys#741.
nmigen/back/rtlil.py diff | blob | history