git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
	Tue, 5 Oct 2010 22:08:18 +0000 (15:08 -0700)
committer	Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
	Tue, 5 Oct 2010 22:08:18 +0000 (15:08 -0700)
commit	a359d7b81adb7f1ca371822bd2df3bac7cda99ba
tree	f31b99d40ceb1b7f489a7cd7853507cdd6108153	tree
parent	fcdd030cbe07d48cbd442d207d53dc3947aff02c	commit \| diff

[xcc,sim] eliminated vectored traps

now, the evec register holds the address that all traps vector to,
and the cause register is set with the trap number.

riscv/insns/mfpcr.h		diff \| blob \| history
riscv/insns/mtpcr.h		diff \| blob \| history
riscv/mmu.h		diff \| blob \| history
riscv/processor.cc		diff \| blob \| history
riscv/processor.h		diff \| blob \| history

Simple-V augmented version of spike

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