gen/fhdl/verilog: list available clock domains on keyerror
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 5 Jun 2017 12:33:46 +0000 (14:33 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 5 Jun 2017 12:33:46 +0000 (14:33 +0200)
commita36986a501978084491148a8f2b860b2e374d452
treeb00374d07506db7fa1ac0cc3dc25c09bf250b947
parent931ea5ac75a6a386bc2c94943ee5271de08eb27c
gen/fhdl/verilog: list available clock domains on keyerror
litex/gen/fhdl/verilog.py