git.libre-soc.org Git - nmigen.git/commit

hdl.ir: call back from Fragment.prepare if a clock domain is missing.

See #57.

nmigen/build/plat.py		diff \| blob \| history
nmigen/compat/fhdl/verilog.py		diff \| blob \| history
nmigen/compat/sim/__init__.py		diff \| blob \| history
nmigen/hdl/ir.py		diff \| blob \| history
nmigen/hdl/xfrm.py		diff \| blob \| history
nmigen/test/test_hdl_ir.py		diff \| blob \| history
nmigen/test/test_sim.py		diff \| blob \| history