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(parent: 75f95c7) | patch
intel/isl: Align non-tiled horizontally by cache line
authorTopi Pohjolainen <topi.pohjolainen@intel.com>
Wed, 28 Jun 2017 09:07:32 +0000 (12:07 +0300)
committerTopi Pohjolainen <topi.pohjolainen@intel.com>
Fri, 21 Jul 2017 21:14:16 +0000 (00:14 +0300)
commita40f0430347c07bf2d5794642fe02f5dd248a473
tree5c3a03cb00d0745d7bae839415596023f3cc2d19tree
parent75f95c710f6fbb1aac36de179bb9eb02d02dad58commit | diff
intel/isl: Align non-tiled horizontally by cache line

in order to support blit engine.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
src/intel/isl/isl.c diff | blob | history