hdl.mem: use more informative signal naming for ports.
authorwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 23:55:02 +0000 (23:55 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 23:55:02 +0000 (23:55 +0000)
commita4183eba69f645a89b3bd865fcf4032ff4a02985
tree938a5fd311e44c58de670ad3f7abe3467a72635c
parent913339c04a0dc17750f98cfbd4b4f57c39992cc9
hdl.mem: use more informative signal naming for ports.
nmigen/hdl/mem.py