Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
authorAli Saidi <Ali.Saidi@ARM.com>
Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)
committerAli Saidi <Ali.Saidi@ARM.com>
Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)
commita432d8e0851de8d090676697e29ca6ed4be64fb7
tree50546c6a98e9d766ad53aa05eb75381ce6d7f298
parent2f40b3b8ae4fddcdd167fc86469254f40736c888
Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
24 files changed:
configs/common/Caches.py
src/cpu/o3/fetch_impl.hh
src/dev/io_device.cc
src/mem/cache/BaseCache.py
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/cache/cache_impl.hh
tests/configs/inorder-timing.py
tests/configs/memtest.py
tests/configs/o3-timing-mp.py
tests/configs/o3-timing.py
tests/configs/pc-simple-atomic.py
tests/configs/pc-simple-timing.py
tests/configs/realview-simple-atomic.py
tests/configs/realview-simple-timing.py
tests/configs/simple-atomic-mp.py
tests/configs/simple-timing-mp.py
tests/configs/simple-timing.py
tests/configs/tsunami-o3-dual.py
tests/configs/tsunami-o3.py
tests/configs/tsunami-simple-atomic-dual.py
tests/configs/tsunami-simple-atomic.py
tests/configs/tsunami-simple-timing-dual.py
tests/configs/tsunami-simple-timing.py