Support NNPC and branch instructions ... Outputs to decoder.cc correctly
authorKorey Sewell <ksewell@umich.edu>
Sun, 19 Feb 2006 04:17:45 +0000 (23:17 -0500)
committerKorey Sewell <ksewell@umich.edu>
Sun, 19 Feb 2006 04:17:45 +0000 (23:17 -0500)
commita48c24b61eedf580645ff0294b225d1e69a9444b
tree6c5337e0e6d801a4b5831f56b74293806b61a767
parentbd175809286e8da64176da977aeb27fc6ff6d272
Support NNPC and branch instructions ... Outputs to decoder.cc correctly

Edits to the CPU model may still need to be made to handle branch likely insts...

arch/isa_parser.py:
    add a NNPC operand ...
arch/mips/isa/base.isa:
    change SPARC to MIPS
arch/mips/isa/decoder.isa:
    typo < to >=
arch/mips/isa/formats/basic.isa:
    spacing
arch/mips/isa/formats/branch.isa:
    add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
    support for NNPC and R31
arch/mips/isa_traits.hh:
    NNPC Addr variable

--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
arch/isa_parser.py
arch/mips/isa/base.isa
arch/mips/isa/decoder.isa
arch/mips/isa/formats/basic.isa
arch/mips/isa/formats/branch.isa
arch/mips/isa/operands.isa
arch/mips/isa_traits.hh