Rename a few reset signals
authorAnton Blanchard <anton@linux.ibm.com>
Sat, 7 Sep 2019 11:08:02 +0000 (21:08 +1000)
committerAnton Blanchard <anton@ozlabs.org>
Sat, 7 Sep 2019 11:33:50 +0000 (21:33 +1000)
commita53ad600145f04348f8270c82dcb3979341c8368
tree54566fd3fa1e50c221d38029d082cc738f54f1d9
parente39400681bfda8671b0a47a18b0052ae6e96893e
Rename a few reset signals

clk -> ext_clk
reset_n -> ext_rst
reset -> rst

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
fpga/arty_a7-35.xdc
fpga/nexys-video.xdc
fpga/nexys_a7.xdc
fpga/toplevel.vhd