x86/Intel: allow MASM representation of embedded broadcast
authorJan Beulich <jbeulich@suse.com>
Fri, 27 May 2022 06:46:29 +0000 (08:46 +0200)
committerJan Beulich <jbeulich@suse.com>
Fri, 27 May 2022 06:46:29 +0000 (08:46 +0200)
commita5748e0d8c50913e3c84a71e7e72faf0f4637021
tree77bce69a458a65e31ffd4eaa41eb8316f560260d
parent811f61d4c453934b765c73bde78fc29ea22c0c7d
x86/Intel: allow MASM representation of embedded broadcast

MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling
DWORD PTR) and alike are to be used there instead. Accept these forms
alongside the original (now legacy) ones.

Acceptance of the original {1to<n>} operand suffix is retained both for
backwards compatibility and to disambiguate VFPCLASSP{S,D,H} and vector
conversions with shrinking element sizes. I have no insight (yet) into
how MASM expects those to be disambiguated.

Adjust some, but not all of the testcases.
24 files changed:
gas/config/tc-i386-intel.c
gas/config/tc-i386.c
gas/testsuite/gas/i386/avx512_bf16.s
gas/testsuite/gas/i386/avx512_bf16_vl.s
gas/testsuite/gas/i386/avx512_fp16.s
gas/testsuite/gas/i386/avx512_fp16_vl.s
gas/testsuite/gas/i386/avx512_vpopcntdq.s
gas/testsuite/gas/i386/avx512bitalg_vl.s
gas/testsuite/gas/i386/avx512dq.s
gas/testsuite/gas/i386/avx512dq_vl.s
gas/testsuite/gas/i386/avx512f.s
gas/testsuite/gas/i386/avx512f_vl.s
gas/testsuite/gas/i386/inval-avx512f.l
gas/testsuite/gas/i386/inval-avx512f.s
gas/testsuite/gas/i386/vp2intersect.s
gas/testsuite/gas/i386/x86-64-avx512_bf16.s
gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.s
gas/testsuite/gas/i386/x86-64-avx512_fp16.s
gas/testsuite/gas/i386/x86-64-avx512_fp16_vl.s
gas/testsuite/gas/i386/x86-64-avx512dq.s
gas/testsuite/gas/i386/x86-64-avx512dq_vl.s
gas/testsuite/gas/i386/x86-64-avx512f.s
gas/testsuite/gas/i386/x86-64-avx512f_vl.s
gas/testsuite/gas/i386/x86-64-vp2intersect.s