git.libre-soc.org Git - gem5.git/commit

author	Mitch Hayenga <mitch.hayenga@arm.com>
	Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)
committer	Mitch Hayenga <mitch.hayenga@arm.com>
	Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)
commit	a5c4eb3de9deb3a71a6a5230a25ff5962e584980
tree	874b659c6a5eaa1316cde9eb82ec7d08badf638a	tree
parent	e255fa053f8d105de8d188077a318124a3aad9ce	commit \| diff

isa,cpu: Add support for FS SMT Interrupts

Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.

23 files changed:

configs/example/fs.py		diff \| blob \| history
configs/example/se.py		diff \| blob \| history
src/arch/alpha/isa/decoder.isa		diff \| blob \| history
src/arch/arm/faults.cc		diff \| blob \| history
src/arch/arm/isa.cc		diff \| blob \| history
src/arch/arm/isa/insts/misc.isa		diff \| blob \| history
src/arch/sparc/isa.cc		diff \| blob \| history
src/arch/sparc/tlb.cc		diff \| blob \| history
src/arch/sparc/ua2005.cc		diff \| blob \| history
src/arch/x86/utility.cc		diff \| blob \| history
src/cpu/BaseCPU.py		diff \| blob \| history
src/cpu/base.cc		diff \| blob \| history
src/cpu/base.hh		diff \| blob \| history
src/cpu/dummy_checker.cc		diff \| blob \| history
src/cpu/intr_control.cc		diff \| blob \| history
src/cpu/kvm/x86_cpu.cc		diff \| blob \| history
src/cpu/minor/execute.cc		diff \| blob \| history
src/cpu/o3/checker.cc		diff \| blob \| history
src/cpu/o3/cpu.cc		diff \| blob \| history
src/cpu/simple/base.cc		diff \| blob \| history
src/dev/x86/i82094aa.cc		diff \| blob \| history
tests/configs/pc-simple-timing-ruby.py		diff \| blob \| history
util/cpt_upgraders/smt-interrupts.py	[new file with mode: 0644]	blob

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