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(parent: cea7e85) | patch
verilog: fix width/sign detection for functions
authorZachary Snow <zach@zachjs.com>
Mon, 30 May 2022 20:45:39 +0000 (16:45 -0400)
committerZachary Snow <zach@zachjs.com>
Mon, 30 May 2022 20:45:39 +0000 (16:45 -0400)
commita650d9079fa4732a6d118f2764d5abc2522a6b37
tree5d4e92924a37dd9f358692d98180e43d71d6d95ctree
parentcea7e85d607304faf36779757df14b4445fe1cfecommit | diff
verilog: fix width/sign detection for functions
CHANGELOG diff | blob | history
frontends/ast/genrtlil.cc diff | blob | history
tests/verilog/func_tern_hint.sv [new file with mode: 0644] blob
tests/verilog/func_tern_hint.ys [new file with mode: 0644] blob