sim: VCD output support
authorSebastien Bourdeauducq <sb@m-labs.hk>
Mon, 21 Sep 2015 13:20:31 +0000 (21:20 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Mon, 21 Sep 2015 13:20:31 +0000 (21:20 +0800)
commita67b4baa0c7eae75217751bd9fea2afcf30d4af8
tree8e05982321fbf3ac2563f99bc6324936065e1baf
parent34ce6b077f4e3bdcc1519b441b3dc437f8060a33
sim: VCD output support
examples/basic/graycounter.py
examples/sim/basic1.py
examples/sim/basic2.py
examples/sim/fir.py
examples/sim/memory.py
migen/sim.py [deleted file]
migen/sim/__init__.py [new file with mode: 0644]
migen/sim/core.py [new file with mode: 0644]
migen/sim/vcd.py [new file with mode: 0644]
migen/test/support.py