Added support for parsing attributes on port connections.
authorMaciej Kurc <mkurc@antmicro.com>
Fri, 31 May 2019 10:24:12 +0000 (12:24 +0200)
committerMaciej Kurc <mkurc@antmicro.com>
Fri, 31 May 2019 12:58:43 +0000 (14:58 +0200)
commita6cadf6318f4eff6197d6c6f0e052c2417689f38
treee287d158a473b27d7723a1b05cc9e3139de007f5
parent90ec2cda4217115fb91206a712befb3e6fa797e5
Added support for parsing attributes on port connections.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
frontends/verilog/verilog_parser.y