i965/gen5: Fix rendering of depth buffers without stencil [v2]

i965/gen5: Fix rendering of depth buffers without stencil [v2]

Fixes the following OGLConform tests on gen5:
    depth-stencil(misc.state_on.depth_int)
    fbo_db_ARBfp(basic.OnlyDepthBuffDrawBufferRender)

The problem was that, if the depth buffer's Mesa format was X8_Z24, then
we emitted the hardware format D24_UNORM_X8. But, on gen5, D24_UNORM_S8
must be emitted.

This bug was introduced by:
    commit d84a180417d1eabd680554970f1eaaa93abcd41e
    Author: Eric Anholt <eric@anholt.net>
    i965: Base HW depth format setup based on MESA_FORMAT, not bpp.

v2: Deref 'intel' directly. Move the branch for newer chipset to top.
    Quote the PRM. As requested by Ken.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43408
Note: This is a candidate for the 8.0 branch.
Reported-by: Xunx Fang <xunx.fang@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>