Fix handling of anyconst/anyseq attrs in VHDL code via Verific
authorClifford Wolf <clifford@clifford.at>
Tue, 15 May 2018 17:27:00 +0000 (19:27 +0200)
committerClifford Wolf <clifford@clifford.at>
Tue, 15 May 2018 17:27:00 +0000 (19:27 +0200)
commita7281930c5877b34e072d90d5ca013f8fda7e2cc
treeb58a6b18cd643cadd0954207447b925d7fa67c66
parent4b6c0e331d0ef4188f8fa2443f8f7999231af052
Fix handling of anyconst/anyseq attrs in VHDL code via Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>
frontends/verific/verific.cc