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(parent: f5e06c2) | patch
Remove some FPGA style signal inits
authorAnton Blanchard <anton@linux.ibm.com>
Tue, 7 Jun 2022 07:38:24 +0000 (17:38 +1000)
committerAnton Blanchard <anton@ozlabs.org>
Tue, 7 Jun 2022 07:38:24 +0000 (17:38 +1000)
commita750365ffa5f07046256d2824520817a6f704214
tree7706b68706e7d0f238c4954146a578bad479d086tree
parentf5e06c2d4bd8faa90a2d3c47ca7ba22343e3aae8commit | diff
Remove some FPGA style signal inits

These don't work on the ASIC flow, so remove them and initialise
them explicitly where required.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
control.vhdl diff | blob | history
core.vhdl diff | blob | history
execute1.vhdl diff | blob | history
gpio.vhdl diff | blob | history
soc.vhdl diff | blob | history
spi_flash_ctrl.vhdl diff | blob | history