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(parent: 87c7d23) | patch
targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 12 Nov 2018 08:45:59 +0000 (09:45 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 12 Nov 2018 08:45:59 +0000 (09:45 +0100)
commita752dafb1400c797e0cc6521d5867e6a37fc5373
treea6e76df1f93a5ddd832447b011abf05cbbbcefbatree
parent87c7d23d16f35499b62f7d7dc2c3cb6fe75d8cd1commit | diff
targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
litex/boards/targets/versa_ecp5.py [new file with mode: 0755] blob
litex/boards/targets/versaecp55g_sdram.py [deleted file] blob | history