projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 6a0f85d) | patch
litex: get verilator simulation working and add sim target as example
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 7 Nov 2015 22:51:37 +0000 (23:51 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 7 Nov 2015 22:51:37 +0000 (23:51 +0100)
commita7756723140c653cf46c7213e34a9f770c7b5845
tree22f30fe8d739d0c85a645ed7579c081232798116tree
parent6a0f85dc423f0c98f483d85f2c4cd57b31270a8bcommit | diff
litex: get verilator simulation working and add sim target as example
MANIFEST.in diff | blob | history
litex/boards/targets/sim.py [new file with mode: 0644] blob
litex/build/sim/verilator.py diff | blob | history
litex/soc/cores/uart/__init__.py diff | blob | history
litex/soc/cores/uart/core.py diff | blob | history