Fix partsel expr bit width handling and add test case
authorClaire Wolf <claire@symbioticeda.com>
Sun, 8 Mar 2020 15:12:12 +0000 (16:12 +0100)
committerClaire Wolf <claire@symbioticeda.com>
Sun, 8 Mar 2020 15:12:12 +0000 (16:12 +0100)
commita7cc4673c3f75f414a82c81a507da5042bba361f
tree616a31593f4be7283072a1e0da6b4187af6f7c04
parentbfeba9ad11847e6a0cbe47f880f3642d5e3a8061
Fix partsel expr bit width handling and add test case

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
frontends/verilog/verilog_parser.y
tests/simple/partsel.v