Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
authorEddie Hung <eddie@fpgeh.com>
Mon, 25 May 2020 21:21:10 +0000 (14:21 -0700)
committerGitHub <noreply@github.com>
Mon, 25 May 2020 21:21:10 +0000 (14:21 -0700)
commita7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4
tree7ad89229bedd897e3dc895084a99197dcf04b8a3
parent59b355fb85cb7cda4a25696850bb3caffce3115f
parent08221edbc15333bcd05ae65cee09c86f875076ab
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy

xilinx: tidy up cells_sim.v a little