i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
authorJason Ekstrand <jason.ekstrand@intel.com>
Wed, 9 May 2018 22:06:13 +0000 (15:06 -0700)
committerJason Ekstrand <jason.ekstrand@intel.com>
Thu, 10 May 2018 01:03:28 +0000 (18:03 -0700)
commita8a740f272a808a2694524b43fc33d2f0c0e3709
tree88cac61454d25170af4a236e572abf13c9ad84d0
parent56766b8515bf73a0f4fc84fad81ba808a520391a
i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL

From the bspec docs for "Indirect State Pointers Disable":

    "At the completion of the post-sync operation associated with this
    pipe control packet, the indirect state pointers in the hardware are
    considered invalid"

So the ISP disable is a post-sync type of operation which means that it
should be combined with a CS stall.  Without this, the simulator throws
an error.

Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable"
Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
src/intel/vulkan/genX_cmd_buffer.c
src/mesa/drivers/dri/i965/brw_pipe_control.c