Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
authorClifford Wolf <clifford@clifford.at>
Wed, 23 Jul 2014 06:40:31 +0000 (08:40 +0200)
committerClifford Wolf <clifford@clifford.at>
Wed, 23 Jul 2014 07:49:43 +0000 (09:49 +0200)
commita8d3a68971ccc4e47c54a906aae374a9a54b1415
treeed08831d07df4e799d881349c36acf76bf277791
parent260c19ec5a3adb292158658dd69a352b9325ab64
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
15 files changed:
backends/blif/blif.cc
backends/edif/edif.cc
frontends/ilang/parser.y
kernel/rtlil.cc
kernel/sigtools.h
passes/abc/abc.cc
passes/fsm/fsm_map.cc
passes/memory/memory_share.cc
passes/opt/opt_clean.cc
passes/proc/proc_mux.cc
passes/sat/eval.cc
passes/sat/miter.cc
passes/sat/share.cc
passes/techmap/extract.cc
passes/techmap/iopadmap.cc