riscv: fix Linux problems with LR and SC ops
authorAlec Roelke <ar4jc@virginia.edu>
Tue, 21 Mar 2017 16:58:25 +0000 (12:58 -0400)
committerAlec Roelke <ar4jc@virginia.edu>
Wed, 5 Apr 2017 20:21:59 +0000 (20:21 +0000)
commita8f1f9811c3fdb1cf59f6d37540ad40e4699561f
tree2fea02557b6c8d72b1c6c5a411f97fd567c67b50
parent6b7d30688d44952fcbb98b3e0f2bfc5155f1f9a5
riscv: fix Linux problems with LR and SC ops

Some of the functions in the Linux toolchain that allocate memory make
use of paired LR and SC instructions, which didn't work properly for
that toolchain.  This patch fixes that so attempting to use those
functions doesn't cause an endless loop of failed SC instructions.

Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7
Reviewed-on: https://gem5-review.googlesource.com/2340
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
src/arch/riscv/SConscript
src/arch/riscv/isa/decoder.isa
src/arch/riscv/isa/formats/amo.isa
src/arch/riscv/isa/formats/mem.isa
src/arch/riscv/locked_mem.cc [new file with mode: 0644]
src/arch/riscv/locked_mem.hh
tests/test-progs/insttest/src/riscv/rv64a.cpp