Ignore celldefine directive in verilog front-end
authorClifford Wolf <clifford@clifford.at>
Wed, 25 Mar 2015 18:46:12 +0000 (19:46 +0100)
committerClifford Wolf <clifford@clifford.at>
Wed, 25 Mar 2015 18:46:12 +0000 (19:46 +0100)
commita923a63a892b8f0c39aa740c8fe207462fe2d8c8
treead5a170887620f00c91672c3d2394306527d7641
parente468d4cc6001b65b9c7e72d3f9c0e9b939ad31b9
Ignore celldefine directive in verilog front-end
frontends/verilog/verilog_lexer.l