uart: rename wishbone to bridge
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 9 May 2015 14:24:28 +0000 (16:24 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 9 May 2015 14:24:28 +0000 (16:24 +0200)
commita99aa9c7fd56e97ebb316ac9b83440f522a622ad
tree8568491355cf6fbe8c1e5ae309f84f9ebf9c5faa
parentfb5397aa82b50e0e6e9c0716e50a01e26e2c740b
uart: rename wishbone to bridge
misoclib/com/liteeth/example_designs/targets/base.py
misoclib/com/litepcie/example_designs/targets/dma.py
misoclib/com/uart/bridge.py [new file with mode: 0644]
misoclib/com/uart/wishbone.py [deleted file]
misoclib/mem/litesata/example_designs/targets/bist.py
misoclib/tools/litescope/example_designs/targets/simple.py