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(parent: dde6dd0) | patch
soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 23 Sep 2019 07:58:47 +0000 (09:58 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 23 Sep 2019 07:58:47 +0000 (09:58 +0200)
commita9acab99b322777133175b54c27f77a9366abfc3
treecfbada67777284a50a68eb234204d29f074f2aadtree
parentdde6dd027bfedc1325f07c88539dc141461b08eacommit | diff
soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals)
litex/soc/integration/soc_core.py diff | blob | history