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(parent: ce5c585) | patch
wishbone/SRAM: make read_only emited verilog code compatible with all tools
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 5 Aug 2019 07:08:56 +0000 (09:08 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 5 Aug 2019 07:08:56 +0000 (09:08 +0200)
commita9fe2788a2308aa59d13cb505d4ad7e10797f45a
tree0c95ab7a5638e4663f7d266bc05a3d8829e6eef4tree
parentce5c58592b95d9115979de8e6a2069dc705ffd31commit | diff
wishbone/SRAM: make read_only emited verilog code compatible with all tools

Quartus was not able to implement ROM correctly, see #228
litex/soc/interconnect/wishbone.py diff | blob | history