[AArch64] Don't allow partial SVE modes in GPRs

[AArch64] Don't allow partial SVE modes in GPRs

With -msve-vector-bits=N, the payload of some partial SVE modes can
be 16 bytes or smaller, which makes them small enough to fit in a
pair of GPRs.  We specifically don't want that, because the payload
is distributed evenly across the SVE register rather than collected
at one end.  Marshalling it into a GPR via register operations would
be expensive.

2019-12-10  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Don't
	allow SVE modes in GPRs.

gcc/testsuite/
	* gcc.target/aarch64/sve/mixed_size_7.c: New test.

From-SVN: r279174