intel/compiler: fix ddy for half-float in Broadwell
authorIago Toral Quiroga <itoral@igalia.com>
Wed, 30 May 2018 10:14:14 +0000 (12:14 +0200)
committerJuan A. Suarez Romero <jasuarez@igalia.com>
Thu, 18 Apr 2019 09:05:18 +0000 (11:05 +0200)
commitaaae24179ff1007776d2f3a5a813f2c52dc83eba
tree7f311bfa8aa6be3b4be8052dac563dd1d1cf6d6c
parent60c7c6d3ba4ab41eec7f48d6266321e10e2e50df
intel/compiler: fix ddy for half-float in Broadwell

Broadwell has restrictions that apply to Align16 half-float that
make the Align16 implementation of this invalid for this platform.
Use the gen11 path for this instead, which uses Align1 mode.

The restriction is not present in cherryview, gen9 or gen10, where
the Align16 implementation seems to work just fine.

v2:
 - Rework the comment in the code, move the PRM citation from the
   commit message to the comment in the code (Matt)
 - Cherryview isn't affected, only Broadwell (Matt)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/intel/compiler/brw_fs_generator.cpp