Fix tests by gating some specify constructs from iverilog
authorEddie Hung <eddie@fpgeh.com>
Thu, 13 Feb 2020 21:43:33 +0000 (13:43 -0800)
committerEddie Hung <eddie@fpgeh.com>
Thu, 27 Feb 2020 18:17:29 +0000 (10:17 -0800)
commitaac309626b4829b8d6efec1854bccf84c0bd0b20
tree0e8a321404b1081106541d16d13cfb7e55908466
parent977262c8033b8778a32d4f29a77c64ea5a2799bd
Fix tests by gating some specify constructs from iverilog
techlibs/xilinx/cells_sim.v