git.libre-soc.org Git - yosys.git/commit

author	Eddie Hung <eddie@fpgeh.com>
	Fri, 4 Oct 2019 18:04:10 +0000 (11:04 -0700)
committer	Eddie Hung <eddie@fpgeh.com>
	Fri, 4 Oct 2019 18:04:10 +0000 (11:04 -0700)
commit	aae2b9fd9c8dc915fadacc24962436dd7aedff36
tree	38ec98224113556a8a5a6d93d5bc2c0cb506286e	tree
parent	9fef1df3c1431cff2e097a10a502f77f04986a60	commit \| diff

Rename abc_* names/attributes to more precisely be abc9_*

52 files changed:

backends/aiger/xaiger.cc		diff \| blob \| history
frontends/aiger/aigerparse.cc		diff \| blob \| history
passes/techmap/abc9.cc		diff \| blob \| history
techlibs/ecp5/Makefile.inc		diff \| blob \| history
techlibs/ecp5/abc9_5g.box	[new file with mode: 0644]	blob
techlibs/ecp5/abc9_5g.lut	[new file with mode: 0644]	blob
techlibs/ecp5/abc9_5g_nowide.lut	[new file with mode: 0644]	blob
techlibs/ecp5/abc9_map.v	[new file with mode: 0644]	blob
techlibs/ecp5/abc9_model.v	[new file with mode: 0644]	blob
techlibs/ecp5/abc9_unmap.v	[new file with mode: 0644]	blob
techlibs/ecp5/abc_5g.box	[deleted file]	blob \| history
techlibs/ecp5/abc_5g.lut	[deleted file]	blob \| history
techlibs/ecp5/abc_5g_nowide.lut	[deleted file]	blob \| history
techlibs/ecp5/abc_map.v	[deleted file]	blob \| history
techlibs/ecp5/abc_model.v	[deleted file]	blob \| history
techlibs/ecp5/abc_unmap.v	[deleted file]	blob \| history
techlibs/ecp5/cells_sim.v		diff \| blob \| history
techlibs/ecp5/synth_ecp5.cc		diff \| blob \| history
techlibs/ice40/Makefile.inc		diff \| blob \| history
techlibs/ice40/abc9_hx.box	[new file with mode: 0644]	blob
techlibs/ice40/abc9_hx.lut	[new file with mode: 0644]	blob
techlibs/ice40/abc9_lp.box	[new file with mode: 0644]	blob
techlibs/ice40/abc9_lp.lut	[new file with mode: 0644]	blob
techlibs/ice40/abc9_model.v	[new file with mode: 0644]	blob
techlibs/ice40/abc9_u.box	[new file with mode: 0644]	blob
techlibs/ice40/abc9_u.lut	[new file with mode: 0644]	blob
techlibs/ice40/abc_hx.box	[deleted file]	blob \| history
techlibs/ice40/abc_hx.lut	[deleted file]	blob \| history
techlibs/ice40/abc_lp.box	[deleted file]	blob \| history
techlibs/ice40/abc_lp.lut	[deleted file]	blob \| history
techlibs/ice40/abc_model.v	[deleted file]	blob \| history
techlibs/ice40/abc_u.box	[deleted file]	blob \| history
techlibs/ice40/abc_u.lut	[deleted file]	blob \| history
techlibs/ice40/cells_sim.v		diff \| blob \| history
techlibs/ice40/synth_ice40.cc		diff \| blob \| history
techlibs/xilinx/Makefile.inc		diff \| blob \| history
techlibs/xilinx/abc9_map.v	[new file with mode: 0644]	blob
techlibs/xilinx/abc9_model.v	[new file with mode: 0644]	blob
techlibs/xilinx/abc9_unmap.v	[new file with mode: 0644]	blob
techlibs/xilinx/abc9_xc7.box	[new file with mode: 0644]	blob
techlibs/xilinx/abc9_xc7.lut	[new file with mode: 0644]	blob
techlibs/xilinx/abc9_xc7_nowide.lut	[new file with mode: 0644]	blob
techlibs/xilinx/abc_map.v	[deleted file]	blob \| history
techlibs/xilinx/abc_model.v	[deleted file]	blob \| history
techlibs/xilinx/abc_unmap.v	[deleted file]	blob \| history
techlibs/xilinx/abc_xc7.box	[deleted file]	blob \| history
techlibs/xilinx/abc_xc7.lut	[deleted file]	blob \| history
techlibs/xilinx/abc_xc7_nowide.lut	[deleted file]	blob \| history
techlibs/xilinx/cells_sim.v		diff \| blob \| history
techlibs/xilinx/synth_xilinx.cc		diff \| blob \| history
techlibs/xilinx/xc6s_brams_bb.v		diff \| blob \| history
techlibs/xilinx/xc7_brams_bb.v		diff \| blob \| history

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