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(parent: 54d7693) | patch
arch-riscv: ignore writes to SXL/UXL fields in status register.
authorNils Asmussen <nils.asmussen@barkhauseninstitut.org>
Mon, 24 Feb 2020 12:47:43 +0000 (13:47 +0100)
committerNils Asmussen <nils.asmussen@barkhauseninstitut.org>
Wed, 29 Apr 2020 11:41:55 +0000 (11:41 +0000)
commitaaf294af5c8e027ba68ddb41198d6f09aee4aeed
tree011066ca6599687de90d249e54b448007fbfc7bdtree
parent54d769308d0ccc5a70db8caa5bb494d2d7d08bd9commit | diff
arch-riscv: ignore writes to SXL/UXL fields in status register.

We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.

Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25651
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
src/arch/riscv/isa.cc diff | blob | history