i965/eu: Emulate F32TO16 and F16TO32 on Broadwell.

i965/eu: Emulate F32TO16 and F16TO32 on Broadwell.

When we combine the Gen4-7 and Gen8+ generators, we'll need to handle
half float packing/unpacking functions somehow.  The Gen8+ generator
code today just emulates the behavior of the Gen7 F32TO16/F16TO32
instructions, including the align16 mode bugs.

Rather than messing with fs_generator/vec4_generator, I decided to just
emulate the instructions at the brw_eu_emit.c layer.

v2: Change gen >= 7 asserts to gen == 7 (suggested by Chris Forbes).
    Fix regressions on Haswell in VS tests due to type assertions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>