radeon/llvm: Extend SI EXEC register support.
authorMichel Dänzer <michel.daenzer@amd.com>
Wed, 29 Aug 2012 16:52:53 +0000 (18:52 +0200)
committerMichel Dänzer <michel@daenzer.net>
Thu, 6 Sep 2012 14:15:44 +0000 (16:15 +0200)
commitab162f80c302307ca331c0182702162ad0e4e9be
treee70b4c25da0a175f76e90636fbd4efdca6e85e13
parent2baaa5c7eb21517f0197bfd91154e9b4886fbb1b
radeon/llvm: Extend SI EXEC register support.

Add 32 bit lo and hi variants, and binary encodings.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
src/gallium/drivers/radeon/SIGenRegisterInfo.pl