aarch64: Add general unpacked SVE conditional binary arithmetic

aarch64: Add general unpacked SVE conditional binary arithmetic

This patch adds support for conditional binary ADD, SUB, MUL, SMAX,
UMAX, SMIN, UMIN, LSL, LSR, ASR, AND, ORR and EOR.  It's not really
possible to split it up further given how the patterns are written.

Min, max and right-shift need the element size rather than the container
size.  The others would work with both, although MUL should be more
efficient when applied to elements instead of containers.

gcc/
	* config/aarch64/aarch64-sve.md (@cond_<SVE_INT_BINARY:optab><mode>)
	(*cond_<SVE_INT_BINARY:optab><mode>_2): Extend from SVE_FULL_I
	to SVE_I.
	(*cond_<SVE_INT_BINARY:optab><mode>_3): Likewise.
	(*cond_<SVE_INT_BINARY:optab><mode>_any): Likewise.
	(*cond_<SVE_INT_BINARY:optab><mode>_2_const): Likewise.
	(*cond_<SVE_INT_BINARY:optab><mode>_any_const): Likewise.

gcc/testsuite/
	* g++.target/aarch64/sve/cond_arith_1.C: New test.
	* g++.target/aarch64/sve/cond_arith_2.C: Likewise.
	* g++.target/aarch64/sve/cond_arith_3.C: Likewise.
	* g++.target/aarch64/sve/cond_arith_4.C: Likewise.
	* g++.target/aarch64/sve/cond_shift_1.C: New test.
	* g++.target/aarch64/sve/cond_shift_2.C: Likewise.
	* g++.target/aarch64/sve/cond_shift_3.C: Likewise.
	* g++.target/aarch64/sve/cond_shift_4.C: Likewise.